1. Technical Field
The present disclosure relates to a method to perform electrical testing and assembly of electronic devices.
The present disclosure also relates to an electronic device comprised in a wafer comprising at least one pad made in an oxide layer covered by a passivation layer and subjected to electrical testing.
The present disclosure also relates to a multichip system in package.
The disclosure particularly, but not exclusively, relates to a method to perform an electrical testing and the assembly of electronic devices, of the type comprising for example a testing on wafer of the “Electrical Wafer Sort” (EWS) type or of the “Final Test” type or, again, testing of embedded devices “System in Package” (SiP), or, again, testing of the “Wafer Level Burn-In” (WLBI) type.
2. Description of the Related Art
As it is well known, one can perform an electrical testing on wafer of the EWS type, by electrically connecting a testing apparatus or tester to the wafer whereon there are the devices (dice or chips) to be tested, also called DUT (Device Under Test). In particular, a probe card is used, which serves as interface between the tester and the wafer. The probe card is a board generally comprising a printed circuit or PCB (Printed Circuit Board) and a plurality of probes (sometimes thousands) which electrically connect the tester to electric terminals of the DUT, usually made of pads.
After having been subjected to the electrical testing EWS, the wafers are cut and, subsequently, during the assembly and the packaging of the single devices, the step is carried out of electric connection between the devices and a support element which is part of the package wherein the devices are embedded, for example a substrate of a PCB or a “leadframe” or other type of support. In particular, the electric connection can be made through “wire bonding”, a technique which forms conductive metallic wires (wire bonds), suitable for connecting the pads of the die to corresponding contact pins of the package. By way of example, FIG. 1A shows a die 1 being electrically connected to a support element 2 through conductive wires 3. FIG. 1B shows a detail of a section of the die 1 comprising, above a substrate 90, at least one oxide layer 4, wherein a pad 5 is made and whereon a passivation layer 6 is formed covering the oxide layer 4. The pad 5 is connected, in correspondence with a portion 5A thereof being free from the passivation layer 6, to the support element 2 of the package, and in particular to a contact portion 7 of the support element 2, through the metallic wire 3.
The use of probes that are positioned on the pads to electrically connect the tester to the wafer implies a damaging of the metal the pads are made of, creating big problems, not only during the testing or “probing”, but especially during the assembly of the die. For example, FIG. 2A shows a DUT 10 comprising a plurality of pads 5, one of which is schematically shown from above in FIG. 2B. In particular, the pad 5 is made of a metallization layer (bond pad metallization) whose outline 13 is marked by a dot line, and this pad 5 is surrounded and partially covered by a passivation layer 6 whose outline 12 is marked by a continuous line corresponding to the opening (passivation opening) which determines the final size of the pad (bond pad size). If the probes of a probe card are placed on the pad 5, this latter can be damaged. The damaging of the exposed metallic surface 5A of this pad 5 is shown in particular in FIG. 2C, in which it is clear that, due to the positioning of a probe 14 on the metallic surface 5A of the pad 5, an irregular region 15 is formed called “probe mark” (which is indicated by blackened areas also in FIG. 2A). It is also to be considered that this damaging can be not limited to the sole metallic surface 5A of the generic pad 5, but extended also to underlying structures of the pad due to the force exercised by the probe on the pad and, after more successive probing, the pad can turn out damaged in different regions of the area being useful to perform the bonding. In particular, this damaging of the surface of the pad can imply a poor adhesion of the bonding metallic wire to the damaged surface, causing the detachment of the wire from the pad, or even a total lack of adhesion and, thus, the impossibility of creating an electric connection through wire bonding.
A further problem arises, when more dice should be embedded inside a package in “stacked” configurations for example of the pyramidal (pyramidal stacked), symmetrical (twin stacked), or with rotated overlapping (overhanging stacked) types, which consist in stacking different dice of different size one above the other, and then creating the connections between the dice and between die and support element of the package through wire bonding.
In fact, in this type of configuration it often occurs that the sizes of the upper die are limited to the position of the pads and of the corresponding wire bonding of the die.
To avoid this problem, the upper die at a suitable distance from the edge of the lower die or use a suitable insulating layer for spacing the lower die from the upper die. FIG. 3 shows, in section, a pyramidal configuration of a first die 1 and of a second die 1′ stacked on the support element 2 of the package, each comprising, above a substrate 90, 90′, an oxide layer 4, 4′ in which a first pad 5, 5′ is made and whereon a passivation layer 6, 6′ is formed covering the oxide layer 4, 4′, except in correspondence with a portion 5A, 5A′ of the first pad 5, 5′. A first metallic wire 3 and a second metallic wire 3′ electrically connect respectively the first pad 5 starting from the portion 5A and the second pad 5′, starting from the portion 5A′, to the support element 2 of the package. The second die 1′ is separated from the first die 1 by an insulating layer 16.
A further problem arises during the performance of a testing of more devices in parallel, for which probe cards with a very high number of probes may be used. This determines an increase of the contacting problems and, thus, of electrical continuity, between the probe card and the wafer, i.e., between the probes and pads of the device to be tested, which causes successive probing on the same devices. In consequence, the electric yield decreases.
The situation in which below the pad metallization layer there is an oxide layer or, even more, a copper metallization layer is particularly sensitive for the probing through probes. In these cases, to avoid the exposure of the copper metallization layer to the oxidizing action of the air, an oxide grid is interposed between the copper metallization layer and the metallization layer of the pad. The pad thus obtained is defined “Studded Pad”, since the presence of this grid makes the surface of the pad as if it were studded. Although the Studded Pad is advantageous in terms of protection of the layers underlying the pad, to form the protection oxide grid of the copper metallization layer, additional process steps are involved, which consequently burden and complicate the manufacturing of the device.
A further problem of the performance of a probing through probes is represented by the mechanical limits of the devices of last generation, which have a high number of pads to be contacted or pads with reduced area or also pads very close to each other, i.e., with reduced “pitch” or “fine pitch”. In particular, for pads of small area, the breakage of the passivation layer surrounding the pad is more likely if probing is performed in an incorrect way. FIG. 4A shows a view from above of a DUT 10 comprising pads 5 wherein the probes 14 create a probe mark 15 (shown by the blackening of the contact sections on the pad 5) and are placed in a correct way (no error). The same DUT 10 is shown in FIGS. 4B, 4C and 4D respectively in the case in which the probes are placed in a non correct way along the axis X (X error), along the axis Y (Y error) or at an angle Θ (Yaw error (theta)).
Moreover, the temperature of the wafer and the temperature of the surrounding environment play a very important role during the performance of the probing. In fact, in case of pads with reduced size and of a high temperature of the wafer, for example much higher than 25 degrees centigrade, it can occur that at least one probe of the probe card, after having contacted the pad, moves on the pad itself due to the thermal expansion of the probe card, causing the breakage of the passivation layer surrounding the pad with a subsequent loss of electric yield. By way of example, FIG. 5A shows the section of one of the pads 5 shown in FIG. 4A, created in an oxide layer 4, covered by a passivation layer 6, in case a probe 14 is correctly placed on it, while FIG. 5B shows the section of the same pad 5, in case the probe 14 has moved (for example due to a thermal expansion of the probe card containing it) on the passivation layer 6 there creating a damaged region 16.
A known method for performing the probing of a device through probes consists in the insertion of suitable pads in the areas that separate the dice from one another, i.e., in the “scribe lines” of the wafer.
A solution of this type is described for example in U.S. Pat. No. 5,956,567, issued on Sep. 21, 1999 to Matsushita Electric Industrial Co., where secondary pads, external with respect to a chip, are inserted inside the scribe lines of a wafer, with the aim of supplying the chip. These secondary pads are connected in parallel, through metallization layers inside the chip, to primary pads which are inside the active area of the chip. In consequence, the primary and secondary pads are about at the same voltage and can be crossed by two currents that are then summed in a common node downstream of the pads themselves. The probing is, therefore, performed by means of probes positioned both on the primary pads and on the secondary pads.
This solution places some additional supply pads outside the chip to avoid area occupation inside the chip having to supply a high supply current. However, the probes being placed also on the primary pads inside the area of the device, this known solution shows the same probe damaging problems previously discussed.
A similar solution is described in U.S. Pat. No. 5,923,047, issued on Jul. 13, 1999, to LSI Logic Corporation, wherein some secondary pads are inserted inside the scribe lines of a wafer, to increase the distance between the adjacent pads (pad pitch). Also according to this known solution, the probing is performed both on the primary pads and on the secondary ones and, in particular, a probe connected to an inner pad of the chip is alternated with a probe connected to an external pad of the chip itself, increasing in this way the distance between two adjacent probes. Although advantageous under several aspects, this known solution shows the main disadvantage of not allowing to simultaneously test two adjacent chips, since it involves skipping at least one chip.
The problems linked to the performance of the probing through the probes of a probe card, placed on pads, are partially overcome by adding a metallization layer to the metallization layers of a device, this additional layer extending from a generic pad up to the passivation layer of the device, separating the area where the probing of the device is performed, or “Probe Region”, from the area which is needed to perform the successive bonding, or “Wire Bond Region”. This technique is usually called POP (acronym from: “Probe Over Passivation”) and solutions of this type are described for example in U.S. Pat. No. 6,844,631, issued on Jan. 18, 2005 to Freescale Semiconductor, Inc. and in the publications “Novel Method of Separating Probe and Wire Bond Regions Without Increasing Die Size”, L. Yong, T. A. Tran, S. Lee, B. Williams, J. Ross, 2003 Electronic Components and Technology Conference; “Problems with Wirebonding on Probe Marks and Possible Solutions”, W. Saute, T. Aoki, T. Hisada, H. Miyai, K. Petrarca, F. Beaulieu, S. Allard, J. Power, M. Agbesi, 2003 Electronic Components and Technology Conference; and “A 44μ Probe Process Characterization and Factory Deployment Using Probe Over Passivation”, B. Williams, T. Angelo, S. S. Yan, T. A. Tran, S. Lee, M. Ruston, 2003 SWTW.
A configuration corresponding to a solution described in U.S. Pat. No. 6,844,631 is freely schematized for example in FIG. 6, in which, in particular, the section of a pad, indicated with 20, is shown, being realized with copper and made in an oxide layer 21 covered by a passivation layer 22, as previously described. Above the pad 20 a metallization layer 23 is shown, in which a first region 24 on the left of the pad 20 covering the passivation layer 22 is devoted to the positioning of the probe for the electrical testing and, then, to the probing (Probe Region), while a second region 25, separated from the first region 24, covering the pad 20 is devoted to the bonding of the electric wires (Wire Bond Region). This configuration, besides solving the bonding problems during the assembly of a device, does not cause any damage of the passivation layer surrounding the pad and allows a remarkable reduction of the area of the pad itself and, consequently, of the device. Moreover, the additional metallization layer can be removed prior to the assembly steps for example through a suitable chemical action.
Although advantageous under several aspects, the solution just described implies that, performing the probing on a metallization layer placed above the passivation layer surrounding the pad, one or more layers underlying the metallization layer can be subjected to breakage. Moreover, the manufacturing process of the devices is complicated by the fact that additional process steps are used to realize the POP and create the additional metallization layer above the passivation layer.
The problems relative to the probing and to the successive step in which the electric connections to the chip are created, are mainly shown when the electrical testing is to be performed on wafers comprising devices with conductive bumps above the pads. For example, FIG. 7A shows the schematic view of a first and of a second DUT 10, 10′ separated by a non-active region of scribe line 26 and FIG. 7B shows the section of an enlarged region of FIG. 7A comprising a pad 5 of the first DUT 10 and a pad 5′ of the second DUT 10′, both realized in an oxide layer 4, covered by a passivation layer 6, in correspondence with which there are respectively a first and a second metallic bump 27, 27′. In this case, to electrically connect the tester which performs the measures to the wafer whereon there are the devices to be tested, a probe card with suitable probes will electrically connect the tester to the bumps of the devices to be tested. Therefore, the probing of the wafer by means of probes is directly carried out on the bumps of the devices, that will be used also subsequently in the assembly step for establishing the electric connections to the support element of the package.
To perform the probing of the bumps, probe cards exist of different type realized with different technologies, for example by employing cantilever probes, vertical probes, pyramidal probes, VS crown probes. All these probe cards however cause in the bumps of the device a damage, that can be possibly reduced, by using suitable technologies and probing processes, as for example the one indicated as “MicroForce Probing Technique” and described in U.S. Pat. No. 7,202,682, issued on Apr. 10, 2007 to FormFactor, Inc., which provides that, after having put probes of the MEMS type (Micro Electro-Mechanical Systems) in contact with the bumps, the chuck of the testing machine is made move obliquely instead of making it rise in a vertical direction, so as to reduce the shift or “scrub” of the probe on the bump without excessively decreasing the intensity of the contact force between the probe and the bump itself. In this way a smaller damage of the bumps is obtained with respect to that obtained with a traditional probing, damage that is however present.
In particular, further to one or more probing the bump is damaged in different areas of its area useful to perform the successive assembly and to create the electric connection. Therefore, the formation of electric connections can result remarkably jeopardized.
Moreover, the performance of the probing on bump is more problematic with respect to that of the probing on pad, since the bumps can show different heights with respect to one another and can be realized with also non planar geometries. And in the structures that show both the pad and the bump, the use of the probes for the probing often creates a damage on both.
To re-distribute the bumps inside the area of the die an optional, additional metallization layer or “redistribution layer” can be used that consists in a metallization layer being realized above the device itself, whose metallic paths start from the pads of the device and are arranged in the area of the device so as to form, in the end, a matrix of pads whereon bumps will be formed. This additional metallization layer is generally covered by a passivation oxide.
Also for the assembly of chips inside a package a redistribution layer can be used made of metallic paths, as described for example in the U.S. Pat. No. 6,861,761 issued on Mar. 1, 2005 to Advanced Semiconductor Engineering, Inc.
However, the creation of a redistribution layer implies additional process steps, that burden the assembly process, indeed.